The design of fast arithmetic logic circuits is an important research topic for reversible and quantum computing. A special challenge in this setting is the computation of standard arithmetical functions without the generation of garbage. The CDKM-adder is a recent garbage-less reversible (quantum) ripple-carry adder. We optimize this design with a novel parallelization scheme wherein m parallel k-bit CDKM-adders are combined to form a reversible mk-bit ripple-block carry adder with logic depth O(m+k) for a minimal logic depth O(\sqrt{mk}), thus improving on the mk-bit CDKM-adder logic depth O(mk). We also show designs for garbage-less reversible set-less-than circuits. We compare the circuit costs of the CDKM and parallel adder in measures of circuit delay, width, gate and transistor count, and find that the parallelized adder offers significant speedups at realistic word sizes with modest parallelization overhead.