Implementing a transputer for FPGA in less than 800 lines of code

Publikation: Bidrag til bog/antologi/rapportKonferencebidrag i proceedings

By utilizing Synchronous Message Exchange (SME) for hardware design, we see that going from a hardware schematic to an implementation becomes a much shorter process. This in turn shifts the focus to the architectural details of the implementation. This is shown by constructing an implementation of the Transputer in SME. This implementation has been made in less than 800 lines of code within the timeframe of ∼4 months, where the majority of the time spent has been on the Transputer architecture. The resulting implementation is suboptimal compared to similar projects. However, since no optimizations have been made, reaching a more reasonable resource consumption and clockrate should be attainable within a few months.

OriginalsprogEngelsk
TitelCommunicating Process Architectures 2017 and 2018, WoTUG-39 and WoTUG-40 - Proceedings of CPA 2017 (WoTUG-39) and Proceedings of CPA 2018 (WoTUG-40)
RedaktørerJan Baekgaard Pedersen, Kevin Chalmers, Jan F. Broenink, Brian Vinter, Kevin Vella, Peter H. Welch, Marc L. Smith, Kenneth Skovhede
Antal sider20
ForlagIMIA and IOS Press
Publikationsdato2019
Sider559-578
ISBN (Elektronisk)9781614999485
DOI
StatusUdgivet - 2019
Begivenhed39th WoTUG Conference on Communicating Process Architectures, CPA 2017 and 40th WoTUG Conference on Communicating Process Architectures, CPA 2018 - Dresden, Tyskland
Varighed: 19 aug. 201822 aug. 2018

Konference

Konference39th WoTUG Conference on Communicating Process Architectures, CPA 2017 and 40th WoTUG Conference on Communicating Process Architectures, CPA 2018
LandTyskland
ByDresden
Periode19/08/201822/08/2018
NavnConcurrent Systems Engineering Series
Vol/bind70
ISSN1383-7575

ID: 241091143