Standard
Implementing a transputer for FPGA in less than 800 lines of code. / Johnsen, Carl Johannes; Skovhede, Kenneth; Vinter, Brian; Quarrie, Lindsay; Dickson, Larry.
Communicating Process Architectures 2017 and 2018, WoTUG-39 and WoTUG-40 - Proceedings of CPA 2017 (WoTUG-39) and Proceedings of CPA 2018 (WoTUG-40). red. / Jan Baekgaard Pedersen; Kevin Chalmers; Jan F. Broenink; Brian Vinter; Kevin Vella; Peter H. Welch; Marc L. Smith; Kenneth Skovhede. IMIA and IOS Press, 2019. s. 559-578 (Concurrent Systems Engineering Series, Bind 70).
Publikation: Bidrag til bog/antologi/rapport › Konferencebidrag i proceedings › Forskning › fagfællebedømt
Harvard
Johnsen, CJ, Skovhede, K, Vinter, B, Quarrie, L & Dickson, L 2019,
Implementing a transputer for FPGA in less than 800 lines of code. i JB Pedersen, K Chalmers, JF Broenink, B Vinter, K Vella, PH Welch, ML Smith & K Skovhede (red),
Communicating Process Architectures 2017 and 2018, WoTUG-39 and WoTUG-40 - Proceedings of CPA 2017 (WoTUG-39) and Proceedings of CPA 2018 (WoTUG-40). IMIA and IOS Press, Concurrent Systems Engineering Series, bind 70, s. 559-578, 39th WoTUG Conference on Communicating Process Architectures, CPA 2017 and 40th WoTUG Conference on Communicating Process Architectures, CPA 2018, Dresden, Tyskland,
19/08/2018.
https://doi.org/10.3233/978-1-61499-949-2-559
APA
Johnsen, C. J., Skovhede, K., Vinter, B., Quarrie, L., & Dickson, L. (2019).
Implementing a transputer for FPGA in less than 800 lines of code. I J. B. Pedersen, K. Chalmers, J. F. Broenink, B. Vinter, K. Vella, P. H. Welch, M. L. Smith, & K. Skovhede (red.),
Communicating Process Architectures 2017 and 2018, WoTUG-39 and WoTUG-40 - Proceedings of CPA 2017 (WoTUG-39) and Proceedings of CPA 2018 (WoTUG-40) (s. 559-578). IMIA and IOS Press. Concurrent Systems Engineering Series Bind 70
https://doi.org/10.3233/978-1-61499-949-2-559
Vancouver
Johnsen CJ, Skovhede K, Vinter B, Quarrie L, Dickson L.
Implementing a transputer for FPGA in less than 800 lines of code. I Pedersen JB, Chalmers K, Broenink JF, Vinter B, Vella K, Welch PH, Smith ML, Skovhede K, red., Communicating Process Architectures 2017 and 2018, WoTUG-39 and WoTUG-40 - Proceedings of CPA 2017 (WoTUG-39) and Proceedings of CPA 2018 (WoTUG-40). IMIA and IOS Press. 2019. s. 559-578. (Concurrent Systems Engineering Series, Bind 70).
https://doi.org/10.3233/978-1-61499-949-2-559
Author
Johnsen, Carl Johannes ; Skovhede, Kenneth ; Vinter, Brian ; Quarrie, Lindsay ; Dickson, Larry. / Implementing a transputer for FPGA in less than 800 lines of code. Communicating Process Architectures 2017 and 2018, WoTUG-39 and WoTUG-40 - Proceedings of CPA 2017 (WoTUG-39) and Proceedings of CPA 2018 (WoTUG-40). red. / Jan Baekgaard Pedersen ; Kevin Chalmers ; Jan F. Broenink ; Brian Vinter ; Kevin Vella ; Peter H. Welch ; Marc L. Smith ; Kenneth Skovhede. IMIA and IOS Press, 2019. s. 559-578 (Concurrent Systems Engineering Series, Bind 70).
Bibtex
@inproceedings{d854f8dca66543e0a35832f977ee7fa3,
title = "Implementing a transputer for FPGA in less than 800 lines of code",
abstract = "By utilizing Synchronous Message Exchange (SME) for hardware design, we see that going from a hardware schematic to an implementation becomes a much shorter process. This in turn shifts the focus to the architectural details of the implementation. This is shown by constructing an implementation of the Transputer in SME. This implementation has been made in less than 800 lines of code within the timeframe of ∼4 months, where the majority of the time spent has been on the Transputer architecture. The resulting implementation is suboptimal compared to similar projects. However, since no optimizations have been made, reaching a more reasonable resource consumption and clockrate should be attainable within a few months.",
keywords = "CSP, FPGA, Hardware, Occam, Processor architecture, SME, Transputer",
author = "Johnsen, {Carl Johannes} and Kenneth Skovhede and Brian Vinter and Lindsay Quarrie and Larry Dickson",
year = "2019",
doi = "10.3233/978-1-61499-949-2-559",
language = "English",
series = "Concurrent Systems Engineering Series",
publisher = "IMIA and IOS Press",
pages = "559--578",
editor = "Pedersen, {Jan Baekgaard} and Kevin Chalmers and Broenink, {Jan F.} and Brian Vinter and Kevin Vella and Welch, {Peter H.} and Smith, {Marc L.} and Kenneth Skovhede",
booktitle = "Communicating Process Architectures 2017 and 2018, WoTUG-39 and WoTUG-40 - Proceedings of CPA 2017 (WoTUG-39) and Proceedings of CPA 2018 (WoTUG-40)",
note = "39th WoTUG Conference on Communicating Process Architectures, CPA 2017 and 40th WoTUG Conference on Communicating Process Architectures, CPA 2018 ; Conference date: 19-08-2018 Through 22-08-2018",
}
RIS
TY - GEN
T1 - Implementing a transputer for FPGA in less than 800 lines of code
AU - Johnsen, Carl Johannes
AU - Skovhede, Kenneth
AU - Vinter, Brian
AU - Quarrie, Lindsay
AU - Dickson, Larry
PY - 2019
Y1 - 2019
N2 - By utilizing Synchronous Message Exchange (SME) for hardware design, we see that going from a hardware schematic to an implementation becomes a much shorter process. This in turn shifts the focus to the architectural details of the implementation. This is shown by constructing an implementation of the Transputer in SME. This implementation has been made in less than 800 lines of code within the timeframe of ∼4 months, where the majority of the time spent has been on the Transputer architecture. The resulting implementation is suboptimal compared to similar projects. However, since no optimizations have been made, reaching a more reasonable resource consumption and clockrate should be attainable within a few months.
AB - By utilizing Synchronous Message Exchange (SME) for hardware design, we see that going from a hardware schematic to an implementation becomes a much shorter process. This in turn shifts the focus to the architectural details of the implementation. This is shown by constructing an implementation of the Transputer in SME. This implementation has been made in less than 800 lines of code within the timeframe of ∼4 months, where the majority of the time spent has been on the Transputer architecture. The resulting implementation is suboptimal compared to similar projects. However, since no optimizations have been made, reaching a more reasonable resource consumption and clockrate should be attainable within a few months.
KW - CSP
KW - FPGA
KW - Hardware
KW - Occam
KW - Processor architecture
KW - SME
KW - Transputer
U2 - 10.3233/978-1-61499-949-2-559
DO - 10.3233/978-1-61499-949-2-559
M3 - Article in proceedings
AN - SCOPUS:85082397095
T3 - Concurrent Systems Engineering Series
SP - 559
EP - 578
BT - Communicating Process Architectures 2017 and 2018, WoTUG-39 and WoTUG-40 - Proceedings of CPA 2017 (WoTUG-39) and Proceedings of CPA 2018 (WoTUG-40)
A2 - Pedersen, Jan Baekgaard
A2 - Chalmers, Kevin
A2 - Broenink, Jan F.
A2 - Vinter, Brian
A2 - Vella, Kevin
A2 - Welch, Peter H.
A2 - Smith, Marc L.
A2 - Skovhede, Kenneth
PB - IMIA and IOS Press
T2 - 39th WoTUG Conference on Communicating Process Architectures, CPA 2017 and 40th WoTUG Conference on Communicating Process Architectures, CPA 2018
Y2 - 19 August 2018 through 22 August 2018
ER -
